Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Two-bit booth multiplier with reduced data path width

Two-bit booth multiplier with reduced data path width

US Patent 5958000 · Granted Sep 28, 1999

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Display substrate and display apparatus2025
Array base plate, display panel and display device2025
Computational structure having multiple stages wherein each stage includes a pai2000
Combined leading one and leading zero anticipator1999
Adder which handles multiple data with different data types1999
Fused floating-point multiply-and-accumulate unit with carry correction1999
Floating-point multiply-and-accumulate unit with classes for alignment and norma1998