Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Continuous byte-stream encoder/decoder using frequency increase and cyclic redundancy check

Continuous byte-stream encoder/decoder using frequency increase and cyclic redundancy check

US Patent 5907566 · Granted May 25, 1999

Estimated economic value: $147,015,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Transmitter tuning using receiver gradient2020
Control of an optical modulator for desired biasing of data and pulse modulators2008
Mapping of packets between links of trunk groups using Mux/Demux devices2004
Coding sublayer for multi-channel media with error correction2004
Bandwidth sharing method2004
Interleaver for burst error correction2003
Physical coding sub-layer for transmission of data over multi-channel media2003
High speed generation and checking of cyclic redundancy check values2003
Method and system for controlling data transfer between a logical switch set and2002
Computer network with a plurality of identically addressed devices2001
Ventilation and cooling control system for modular platforms2001
Voltage regulation and power switching system2001