{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Method and apparatus for pipelining an error detection algorithm on an n-bit word stored in memory", "item": "https://www.patentleaderboard.com/patent/5878059"}]}
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Home › Method and apparatus for pipelining an error detection algorithm on an n-bit word stored in memory

Method and apparatus for pipelining an error detection algorithm on an n-bit word stored in memory

US Patent 5878059 · Granted Mar 2, 1999

Estimated economic value: $507,454,000 ⓘ

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