Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for operating digital static CMOS components in a very low voltage mode during power-down

Method and apparatus for operating digital static CMOS components in a very low voltage mode during power-down

US Patent 5852737 · Granted Dec 22, 1998

Estimated economic value: $16,502,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Multi-mode home terminal system that utilizes a single embedded general purpose/1993
High resolution, multi-frequency digital phase-locked loop1993
Method and apparatus for observing internal memory-mapped registers1993