Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for fast evaluation of dynamic CMOS logic circuits

Method and apparatus for fast evaluation of dynamic CMOS logic circuits

US Patent 5825208 · Granted Oct 20, 1998

Estimated economic value: $18,639,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Formulations comprising hydralazine, prazosin, torsemide, spironolactone, and/or2023
Subcutaneous administration of modified factor IX polypeptides and treatment of 2022
Modified factor VII polypeptides for subcutaneous administration and on-demand t2022
Implementing write ports in register-file array cell2021
Formulations comprising aldosterone receptor antagonists and treatments using sa2021
Fast multi-width instruction issue in parallel slice processor2021
Propagating constants of structured soft blocks while preserving the relative pl2020
Operation of a multi-slice processor implementing load-hit-store handling2020
Merging status and control data in a reservation station2020
Methods of treatment comprising torsemide2020
Treatments and formulations comprising Torsemide2019
Broadcasting messages between execution slices for issued instructions indicatin2019