{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Semiconductor memory device having bit lines widely spaced without sacrifice of narrow pitch of source/drain lines of memory cells", "item": "https://www.patentleaderboard.com/patent/5790450"}]}

Home › Semiconductor memory device having bit lines widely spaced without sacrifice of narrow pitch of source/drain lines of memory cells

Semiconductor memory device having bit lines widely spaced without sacrifice of narrow pitch of source/drain lines of memory cells

US Patent 5790450 · Granted Aug 4, 1998

Estimated economic value: $10,000 ⓘ

Assignee

Nec

Inventors

Teiichiro Nishizaka (12 patents)
Kazuyuki Yamasaki (67 patents)

View full patent text on Google Patents →