Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for correcting a multilevel cell memory by using interleaving

Method and apparatus for correcting a multilevel cell memory by using interleaving

US Patent 5754566 · Granted May 19, 1998

Estimated economic value: $58,580,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Current sensing scheme for non-volatile memory2010
Two transistor wordline decoder output driver2009
Block-level read while write method and apparatus2004
Kicker for non-volatile memory drain bias2004
Load for non-volatile memory drain bias2003
Drain bias for non-volatile memory2003
Bit map addressing schemes for flash memory2002
Local sensing of non-volatile memory2002
Sample and hold voltage reference source2002
Interface for flash EEPROM memory arrays2001
Dynamic single bit per cell to multiple bit per cell memory2000
Sensing scheme for flash memory with multilevel cells1998