Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of making a transistor having a deposited dual-layer spacer structure

Method of making a transistor having a deposited dual-layer spacer structure

US Patent 5714413 · Granted Feb 3, 1998

Estimated economic value: $122,866,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Methods of transferring micro light emitting diode devices using electromagnetic2025
Apparatus for transferring plurality of micro devices and methods of fabrication2022
Non-planar semiconductor device having omega-fin with doped sub-fin region and m2022
Electromagnetic tool for transferring micro devices and methods of transfer2021
Electromagnetic tool for transferring micro devices and methods of fabrication2021
Non-planar semiconductor device having omega-fin with doped sub-fin region and m2019
Antireflective coatings for via fill and photolithography applications and metho2015
Dielectric spacers for metal interconnects and method to form the same2013
Antireflective coatings for via fill and photolithography applications and metho2011
Dielectric spacers for metal interconnects and method to form the same2011
Soluble hard mask for interlayer dielectric patterning2010
Dielectric spacers for metal interconnects and method to form the same2010