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Home › Method for preventing delamination of interlevel dielectric layer over FET P.sup.+ doped polysilicon gate electrodes on semiconductor integrated circuits

Method for preventing delamination of interlevel dielectric layer over FET P.sup.+ doped polysilicon gate electrodes on semiconductor integrated circuits

US Patent 5707896 · Granted Jan 13, 1998

Estimated economic value: $2,771,000 ⓘ

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