Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and apparatus for reducing delays following the execution of a branch instruction in an instruction pipeline

Method and apparatus for reducing delays following the execution of a branch instruction in an instruction pipeline

US Patent 5696958 · Granted Dec 9, 1997

Estimated economic value: $21,338,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Automated processor generation system and method for designing a configurable pr2017
System and method of designing instruction extensions to supplement an existing 2014
System and method of customizing an existing processor design having an existing2014
Automated processor generation system and method for designing a configurable pr2012
Providing extended precision in SIMD vector arithmetic operations2011
Automated processor generation system for designing a configurable processor and2011
Alignment and ordering of vector elements for single instruction multiple data p2010
Providing extended precision in SIMD vector arithmetic operations2009
Automated processor generation system and method for designing a configurable pr2008
Prefetching hints2008
Vector co-processor for configurable and extensible processor architecture2008
Method and apparatus for adding advanced instructions in an extensible processor2008