Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Single PAL circuit generating system clock and control signals to minimize skew

Single PAL circuit generating system clock and control signals to minimize skew

US Patent 5426772 · Granted Jun 20, 1995

Estimated economic value: $87,007,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Component array adapter2003
Automatic clock calibration circuit2001
Circuitry for resolving multiple asynchronous state inputs1996
Data instrumentation system having circuitry for resolving multiple asynchronous1996
Method and apparatus for measuring frequency and high/low time of a digital sign1995
Method and apparatus for testing frequency symmetry of digital signals1995
Method and apparatus for synchronizing periodic sync pulse generations by a numb1995
RAM addressing apparatus with lower power consumption and less noise generation1995
Method and apparatus for deskewing/resynchronizing data slices with variable ske1995
Method and apparatus for digitally compensating digital clock skew for high spee1994