Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Fully testable chip having self-timed memory arrays

Fully testable chip having self-timed memory arrays

US Patent 5394403 · Granted Feb 28, 1995

Estimated economic value: $10,234,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Fault injection event detection at a chip and related systems, method and device2023
Web based template reporting system2018
Enhancement of multi-lingual business indicia through curation and synthesis of 2016
Ascribing actionable attributes to data that describes a personal identity2016
System and method for recursively traversing the internet and other sources to i2016
Web based template reporting system2016
System for non-deterministic disambiguation and qualitative entity matching of g2015
System and method for aggregation and association of professional affiliation da2015
Ascribing actionable attributes to data that describes a personal identity2013
Method for alleviating marangoni flow-induced print defects in ink-jet printing1997