Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Low-power, jitter-compensated phase locked loop and method therefor

Low-power, jitter-compensated phase locked loop and method therefor

US Patent 5373255 · Granted Dec 13, 1994

Estimated economic value: $7,472,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Signal path linearization2019
Microprocessor-assisted calibration for analog-to-digital converter2017
Efficient calibration of errors in multi-stage analog-to-digital converter2016
Foreground techniques for comparator calibration2014
Background techniques for comparator calibration2014
Line-powered network interface device2007
System and method for reliably communicating telecommunication information2006
System and method for interfacing telephony voice signals with a broadband acces2005
Backplane architecture for a telecommunications system chassis2005
Method and apparatus for echo cancellation updates in a multicarrier transceiver2004
Method and apparatus for echo cancellation updates in a multicarrier transceiver2004
Method for allocating data and power in a discrete, multi-tone communication sys2001