Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › CMOS-based peak detector for fast-in, slow-out min/max detection

CMOS-based peak detector for fast-in, slow-out min/max detection

US Patent 5321656 · Granted Jun 14, 1994

Estimated economic value: $2,689,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Array architecture for long record length fast-in slow-out (FISO) analog memory2000
Clock signal generator for a logic analyzer controlled to lock both edges to a r1999
Signal sampling circuit with redundancy1996
High speed sample and hold signal generator1994
Analog-to-digital converter employing multiple parallel switching capacitor circ1994
Fiso analog signal acquisition system employing CCD array storage1993
Analog acquisition system including a high speed timing generator1992
Accurate delay generator having a compensation feature for power supply voltage 1991
Serial dynamic memory shift register1990
Vertical punch-through cell1989
Refresh cell for a random access memory1989
Voltage sustainer for above V.sub.CC level signals1988