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Home › System and method for preserving instruction granularity when translating program code from a computer having a first architecture to a computer having a second reduced architecture during the occurrence of interrupts due to asynchronous events

System and method for preserving instruction granularity when translating program code from a computer having a first architecture to a computer having a second reduced architecture during the occurrence of interrupts due to asynchronous events

US Patent 5307504 · Granted Apr 26, 1994

Estimated economic value: $2,921,000 ⓘ

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