Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Clock signal latency elimination network

Clock signal latency elimination network

US Patent 5272729 · Granted Dec 21, 1993

Estimated economic value: $18,906,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Efficient calibration of a low power parallel data communications channel2017
Circuit for detecting structural defects in an integrated circuit chip, methods 2017
System interconnect dynamic scaling handshake using spare bit-lane2017
System interconnect dynamic scaling handshake using spare bit-lane2017
System interconnect dynamic scaling by lane width and operating frequency balanc2016
System interconnect dynamic scaling by lane width and operating frequency balanc2016
Bus interface optimization by selecting bit-lanes having best performance margin2016
Efficient calibration of a low power parallel data communications channel2016
System interconnect dynamic scaling by predicting I/O requirements2016
System interconnect dynamic scaling by predicting I/O requirements2016
Configurable differential to single ended IO2016
Bus interface optimization by selecting bit-lanes having best performance margin2016