Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like

Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like

US Patent 5259006 · Granted Nov 2, 1993

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System and method for managing property2012
Method and apparatus for generating optimized functional macros2000