Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Digital self-calibrating delay line and frequency multiplier

Digital self-calibrating delay line and frequency multiplier

US Patent 5216301 · Granted Jun 1, 1993

Estimated economic value: $2,418,000 ⓘ

Assignee

No assignee recorded.

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Channel inductor2018
Ceramic lined channel inductor2016
Adaptive current limiter and dimmer system including the same2015
Power factor converter and method2013
Bipolar electrosurgical end effectors1999
Sine wave generator utilizing variable encoding for different frequency signals1994
Sine wave generator utilizing variable encoding for different frequency signals1994
Circuit to selectively process dip switches onto bus lines1992
Matrix-vector multiplication apparatus1992
Optical pattern extracting apparatus1992
Image correlation calculation apparatus1991
Apparatus for detecting primitive patterns in an image1991