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Home › Method for improving the electrical erase characteristics of floating gate memory cells by immediately depositing a protective polysilicon layer following growth of the tunnel or gate oxide

Method for improving the electrical erase characteristics of floating gate memory cells by immediately depositing a protective polysilicon layer following growth of the tunnel or gate oxide

US Patent 5106772 · Granted Apr 21, 1992

Estimated economic value: $53,071,000 ⓘ

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