{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Redundancy CAM using word line from memory", "item": "https://www.patentleaderboard.com/patent/5046046"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Redundancy CAM using word line from memory

Redundancy CAM using word line from memory

US Patent 5046046 · Granted Sep 3, 1991

Estimated economic value: $43,376,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Current sensing scheme for non-volatile memory2010
Two transistor wordline decoder output driver2009
Block-level read while write method and apparatus2004
Kicker for non-volatile memory drain bias2004
Load for non-volatile memory drain bias2003
Drain bias for non-volatile memory2003
Bit map addressing schemes for flash memory2002
Bit map addressing schemes for flash memory2002
Local sensing of non-volatile memory2002
Sample and hold voltage reference source2002
Dynamic single bit per cell to multiple bit per cell memory2000
Sensing scheme for flash memory with multilevel cells1998