Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of fabricating a semiconductor device using a tri-layer structure and conductive sidewalls

Method of fabricating a semiconductor device using a tri-layer structure and conductive sidewalls

US Patent 4994400 · Granted Feb 19, 1991

Estimated economic value: $1,423,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Electrode for plasma processing chamber2021
Sequential station tool for wet processing of semiconductor wafers2014
Sequential station tool for wet processing of semiconductor wafers2013
Adjustable chemical vapor deposition showerhead assembly2012
Process for electroplating metals into microscopic recessed features2011
Sequential station tool for wet processing of semiconductor wafers2011
Sensor for measuring liquid contaminants in a semiconductor wafer fabrication pr2010
Methods and apparatus for controlled-angle wafer positioning2010
Sequential station tool for wet processing of semiconductor wafers2007
Methods and apparatus for controlled-angle wafer positioning2006
Liquid detection end effector sensor and method of using the same2006
Clamshell apparatus with crystal shielding and in-situ rinse-dry2006