Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Triple-implanted drain in transistor made by oxide sidewall-spacer method

Triple-implanted drain in transistor made by oxide sidewall-spacer method

US Patent 4878100 · Granted Oct 31, 1989

Estimated economic value: $1,351,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Method and apparatus for a filament channel pass gate ferroelectric capacitor me1993
Method of assembling compact silicon module for high density integrated circuits1992
Method and apparatus for a filament channel pass gate ferroelectric capacitor me1992
Compact silicon module for high density integrated circuits1991
Integrated circuit metallization with reduced electromigration1990
Method of making a metal-gate MOS VLSI device1989
Integrated circuit metallization with reduced electromigration1988
Interconnect and contact system for metal-gate MOS VLSI devices1988
Metal gate, interconnect and contact system for VLSI devices1987
Laser make-link programming of semiconductor devices1987
Process for making molybdenum gate and titanium silicide contacted MOS transisto1987
Molybdenum-metal mask for definition and etch of oxide-encapsulated metal gate1986