{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Translation of virtual and real addresses to system addresses", "item": "https://www.patentleaderboard.com/patent/4654790"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Translation of virtual and real addresses to system addresses

Translation of virtual and real addresses to system addresses

US Patent 4654790 · Granted Mar 31, 1987

Estimated economic value: $16,228,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Page invalidation processing with setting of storage key to predefined value2016
Page invalidation processing with setting of storage key to predefined value2015
Deferred page clearing in a multiprocessor computer system2014
Reducing interprocessor communications pursuant to updating of a storage key2013
Reducing interprocessor communications pursuant to updating of a storage key2013
Processing of self-modifying code in multi-address-space and multi-processor sys2010
Queue or stack based cache entry reclaim method2008
Processing of self-modifying code in multi-address-space and multi-processor sys2008
Clock distribution system for reducing clock skew between processors in a dual s1996
Net verification method and apparatus1995
Computer system architecture implementing split instruction and operand cache li1992
Apparatus for storing data with deferred uncorrectable error reporting1988