Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Noise reduction during testing of integrated circuit chips

Noise reduction during testing of integrated circuit chips

US Patent 4644265 · Granted Feb 17, 1987

Estimated economic value: $16,020,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Electronic and optical devices and methods of forming these devices2006
Capacitor having improved electrodes2005
Three dimensional package and architecture for high performance computer2001
Three dimensional package and architecture for high performance computer1999
Three dimensional package and architecture for high performance computer1998
On-chip temperature sensing system1997
Three dimensional package and architecture for high performance computer1996
Semiconductor chip interposer module with engineering change wiring and distribu1993
Low power push pull driver1992
Method and apparatus for detecting faults in differential current switching logi1990
Oscillation prevention during testing of integrated circuit logic chips1985
On-chip Delta-I noise clamping circuit1983