{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Circuitry for reducing parasitic coupling in core memory", "item": "https://www.patentleaderboard.com/patent/4300214"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Circuitry for reducing parasitic coupling in core memory

Circuitry for reducing parasitic coupling in core memory

US Patent 4300214 · Granted Nov 10, 1981

Estimated economic value: $1,355,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Packaging structure and method for solid electrolyte capacitors1995
Solid electrolyte capacitor and method of making1992
Solid electrolyte capacitor and method of making1992
Solid electrolyte capacitor and method of making1991
Non-volatile semiconductor memory with SCRAM hold cycle prior to SCRAM-to-E.sup.1990
Soft write apparatus and method for nondestructive readout core memory1989
Fast, non-volatile semiconductor/bubble memory with temperature-compensated magn1985
Field effect transistor core memory switching system and method1984