Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Gate-induced drain leakage pre-charge in sub-block mode for three or more tier non-volatile memory structure

Gate-induced drain leakage pre-charge in sub-block mode for three or more tier non-volatile memory structure

US Patent 12482528 · Granted Nov 25, 2025

Assignee

No assignee recorded.

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Clamping-kneading massage structure and massager2025
Display panel, control methods, and display device2025
Negative word line enabled pre-boosting strategy to improve NAND program perform2025
Anti-CTLA4 and anti-PD-1 bifunctional antibody, pharmaceutical composition there2025
Display device2025
Information processing method and apparatus for obtaining a display result by a 2025
Non-volatile memory with efficient precharge in sub-block mode2025
Sidelink data packet sending and receiving method and communication apparatus2025
Non-volatile memory with dummy word line assisted pre-charge2025
Non-volatile memory with dummy word line assisted pre-charge2025
Compute in memory three-dimensional non-volatile NAND memory for neural networks2025
Asymmetric VREADK to reduce neighboring word line interference in a memory devic2025