Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › In-memory computation system with built-in subtraction mode for handling matrix vector multiplication of signed feature data and signed computational weight data

In-memory computation system with built-in subtraction mode for handling matrix vector multiplication of signed feature data and signed computational weight data

US Patent 12355443 · Granted Jul 8, 2025

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

In-memory computation device having improved drift compensation2025
In-memory computation device having improved drift compensation2025
In-memory computation device having improved drift compensation2025
Method for storing information in a coded manner in non-volatile memory cells, d2025
Voltage regulator comprising a charge pump circuit2025
Voltage regulator comprising a charge pump circuit2025
Voltage regulator circuit for a switching circuit load2025
Voltage regulator circuit for a switching circuit load2025
Voltage regulator circuit for a switching circuit load2025
Sense amplifier architecture for a non-volatile memory storing coded information2025
Signed and binary weighted computation for an in-memory computation system2025
Signed and binary weighted computation for an in-memory computation system2025