Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Enabling secure state-clean during configuration of partial reconfiguration bitstreams on FPGA

Enabling secure state-clean during configuration of partial reconfiguration bitstreams on FPGA

US Patent 12346489 · Granted Jul 1, 2025

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Computational storage in a function-as-a-service architecture2025
Multi-purpose interface for configuration data and user fabric data2025
Technologies for secure I/O with accelerator devices2025
Attestation of operations by tool chains2025
Interconnect architecture with silicon interposer and EMIB2025
Enabling late-binding of security features via configuration security controller2025
Enabling late-binding of security features via configuration security controller2025
Enabling late-binding of security features via configuration security controller2025
Supply voltage control systems and methods for integrated circuits2025
Intent-based orchestration in heterogenous compute platforms2025
Providing a partial reconfiguration (PR) bitstream to a cloud service provider f2025
Providing a partial reconfiguration (PR) bitstream to a cloud service provider f2025