Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Programming frequently read data to low latency portions of a solid-state storage array

Programming frequently read data to low latency portions of a solid-state storage array

US Patent 12135878 · Granted Nov 5, 2024

Estimated economic value: $26,483,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Managing permissions for processing input/output (I/O) operations in a storage s2025
Selectable write paths with power loss protection2025
Storage system with dynamic data management functions2025
Data storage system with managed flash2025
Determining remaining hardware life in a storage device2025
Preserving data in a storage system operating in a reduced power mode2025
Data block allocation for storage system2025
Optimized read request processing for relocated data2025
Optimized read request processing for relocated data2025
Latency reduction of flash-based devices using programming interrupts2025
Recover corrupted data through speculative bitflip and cross-validation2025
Page write requirements for a distributed storage system2025