Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Embedded semiconductor region for latch-up susceptibility improvement

Embedded semiconductor region for latch-up susceptibility improvement

US Patent 11973080 · Granted Apr 30, 2024

Estimated economic value: $18,610,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Integrated circuit device and method for ESD protection2025
Method and system for latch-up prevention2025
Integrated circuit device and method2025
Method of producing a vapor-permeable and liquid-impermeable porous structure el2025
Snapback electrostatic discharge (ESD) circuit, system and method of forming the2025
Electrostatic discharge circuit and method of operating same2025
Capacitor cell and structure thereof2024
Capacitor cell and structure thereof2024
Method of making semiconductor device electrostatic discharge diode2024
Integrated circuit with electrostatic discharge protection2024
Device and method for operating the same2024
Integrated circuit device, method, and system2024