Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Mitigation of transistor reliability degradation within memory circuits

Mitigation of transistor reliability degradation within memory circuits

US Patent 11972823 · Granted Apr 30, 2024

Estimated economic value: $239,224,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Identifying unusable memory blocks based on zeros-ones imbalance in memory reado2025
Efficient programming schemes in a nonvolatile memory2023
Identifying failure type in NVM programmed in SLC mode using a single programmin2022
Handling malfunction in a memory system comprising a nonvolatile memory by monit2021
Schemes for protecting data in NVM device using small storage footprint2021
Recovering from failure in programming a nonvolatile memory2020
Efficient post programming verification in a nonvolatile memory2020
Tamper-proof storage using signatures based on threshold voltage distributions2020
Recovery of data read from memory with unknown polarity2019
Tamper-proof storage using signatures based on threshold voltage distributions2019
Memory block usage based on block location relative to array edge2019
Dynamic control of power consumption based on memory device activity2019