Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › On-chip device testing circuit that generates noise on power bus of memory device

On-chip device testing circuit that generates noise on power bus of memory device

US Patent 11915739 · Granted Feb 27, 2024

Estimated economic value: $14,682,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Pulse detection in microelectronic devices, and related devices, systems, and me2024
Systems and techniques for jitter reduction2024
Time to digital circuitry with error protection scheme2023
Time to digital circuitry with error protection scheme2023
Glitch detection in microelectronic devices, and related devices, systems, and m2023
Deterministic jitter generator with controllable probability distribution2022
Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall 2021
Electronic device with a timing adjustment mechanism2021
Techniques for clock signal jitter generation2021
Circuits, apparatuses, and methods for frequency division2020
Apparatuses and methods for maintaining a duty cycle error counter2020
Electronic device with a timing adjustment mechanism2020