Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array

Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array

US Patent 11844204 · Granted Dec 12, 2023

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Methods for fabricating a 3-dimensional memory structure of nor memory strings2025
Methods for fabricating a 3-dimensional memory structure of nor memory strings2025
Wound healing analysis and tracking2025
Bearing monitoring/analysis system2025
High capacity memory circuit with low effective latency2025
Micro flow measuring device and method based on mass method2025
Determining offsets for memory read operations2025
Device with embedded high-bandwidth, high-capacity memory using wafer bonding2025
Three-dimensional memory string array of thin-film ferroelectric transistors for2025
Three-dimensional memory string array of thin-film ferroelectric transistors for2025
Pet bath machine2025
Predictive maintenance of dynamic leaf guide based on deep learning2025