Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methods and circuits for reducing clock jitter

Methods and circuits for reducing clock jitter

US Patent 11831323 · Granted Nov 28, 2023

Estimated economic value: $57,010,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Self-aligning interconnect for a digital system2025
Clock generator system with dynamic frequency crossover2025
Live offset cancellation of the decision feedback equalization data slicers2024
Pattern detection based parameter adaptation2024
Pattern detection based parameter adaptation2024
Methods and circuits for decision-feedback equalization using compensated decisi2023
Phase-locked loop with phase information multiplication2023
Matched digital-to-analog converters2023
Offset calibration for successive approximation register analog to digital conve2023
Live offset cancellation of the decision feedback equalization data slicers2023
Pattern detection based parameter adaptation2023
Pattern detection based parameter adaptation2023