Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System and method for managing faults in integrated circuits

System and method for managing faults in integrated circuits

US Patent 11797373 · Granted Oct 24, 2023

Estimated economic value: $22,478,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Architecture for managing asynchronous resets in a system-on-a-chip2025
System and method for managing secure memories in integrated circuits2024
Fault recovery system for functional circuits2024
Method and system for managing fault recovery in system-on-chips2023
Method and system for managing fault recovery in system-on-chips2023
Testing of lockstep architecture in system-on-chips2023
System and method for controlling faults in system-on-chip2022
System and method for controlling faults in system-on-chip2022
Clock sweeping system2022
Clock sweeping system2022
Configurable memory architecture for computer processing systems2022
System and method for testing critical components on system-on-chip2022