Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Stacked memory device system interconnect directory-based cache coherence methodology

Stacked memory device system interconnect directory-based cache coherence methodology

US Patent 11741012 · Granted Aug 29, 2023

Estimated economic value: $10,098,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Packet routing between memory devices and related apparatuses, methods, and memo2025
Apparatuses and methods for logic/memory devices2025
Comparison operations in memory2025
Memory access determination2025
Unauthorized memory access mitigation2025
Conditional write back scheme for memory2025
Apparatuses and methods for memory alignment2025
Data transfer with a bit vector operation device2025
Apparatuses and methods for scatter and gather2025
Generating and executing a control flow2025
Host-based error correction2025
Neuron using posits2024