Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methods of incorporating leaker devices into capacitor configurations to reduce cell disturb, and capacitor configurations incorporating leaker devices

Methods of incorporating leaker devices into capacitor configurations to reduce cell disturb, and capacitor configurations incorporating leaker devices

US Patent 11676768 · Granted Jun 13, 2023

Estimated economic value: $11,975,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Memory device having tiers of 2-transistor memory cells2025
Vertical transistor, integrated circuitry, method of forming a vertical transist2025
Vertical transistor, integrated circuitry, method of forming a vertical transist2025
Ferroelectric transistors and assemblies comprising ferroelectric transistors2025
Memory device having shared read/write data line for 2-transistor vertical memor2025
Memory device having 2-transistor vertical memory cell and shared channel region2025
Memory device assembly with non-impinged leaker devices2025
Differential storage in memory arrays2025
Transistors and memory arrays2025
Memory device assembly with a leaker device2025
Memory device having 2-transistor memory cell and access line plate2025
Apparatus and method including memory device having 2-transistor vertical memory2025