Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System and method for mapping memory addresses to locations in set-associative caches

System and method for mapping memory addresses to locations in set-associative caches

US Patent 11620225 · Granted Apr 4, 2023

Estimated economic value: $116,209,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System and method for large memory transaction (LMT) stores2025
Circuit and method for translation lookaside buffer (TLB) implementation2024
System and method for large memory transaction (LMT) stores2024
Configuration cache for the ARM SMMUv32022
System and method for mapping memory addresses to locations in set-associative c2022
Instruction ordering for in-progress operations2019
Sharing resources in a multi-context computing system2019
Approach for interfacing a pipeline with two or more interfaces in a processor2018
Instruction ordering for in-progress operations2018
Distributing resource requests in a computing system2017
Caching TLB translations using a unified page table walker cache2016