Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › System interconnect architecture using dynamic bitwise switch and low-latency input/output

System interconnect architecture using dynamic bitwise switch and low-latency input/output

US Patent 11610040 · Granted Mar 21, 2023

Estimated economic value: $322,373,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System and method for managing serial lanes in a multi-user emulation system2025
Embedded processor architecture with shared memory with design under test2024
Emulation system supporting representation of four-state signals2024
Systems and methods for enhanced compression of trace data in an emulation syste2023
Systems and methods for intercycle gap refresh and backpressure management2022
Emulator synchronization subsystem with enhanced slave mode2022
Architecture and methodology for tuning clock phases to minimize latency in a se2022
Emulation system supporting computation of four-state combinational functions2022
Pseudorandom keephot instructions to mitigate large load steps during hardware e2022
Tiled datamesh architecture2022
Systems and methods for handling DPI messages outgoing from an emulator system2022
Systems and methods for communicating with clients with non-deterministic respon2022