Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Block level design method for heterogeneous PG-structure cells

Block level design method for heterogeneous PG-structure cells

US Patent 11574108 · Granted Feb 7, 2023

Estimated economic value: $13,972,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Semiconductor structure including boundary header cell and method for manufactur2025
Standard cell design with dummy padding2025
Standard cell design with dummy padding2025
Integrated circuit and method of forming the same2025
Structure and method of rectangular cell in semiconductor device2025
Diagonal torus network2025
Integrated circuit device and method2025
Timing driven cell swapping2025
Systems and methods for integrated circuit layout2025
Conductive line structures and method of forming same2025
System and method of verifying slanted layout components2025
Integrated circuit with mixed row heights2025