Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Integrated circuit fin layout method

Integrated circuit fin layout method

US Patent 11568122 · Granted Jan 31, 2023

Estimated economic value: $8,861,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Package structure, semiconductor device and manufacturing method thereof2025
Package structure, semiconductor device and manufacturing method thereof2025
Self-aligned scheme for semiconductor device and method of forming the same2025
FinFET device having a channel defined in a diamond-like shape semiconductor str2025
Method of manufacturing a semiconductor device2025
Integrated circuit and method for forming the same2025
Method of forming semiconductor device having segmented interconnect2025
Metal cut region location method2025
Metal cut region location method2025
Devices with reduced capacitances2025
Semiconductor device including parallel configuration2025
Semiconductor device including parallel configuration2025