Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Pulsing scheme for a ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects

Pulsing scheme for a ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects

US Patent 11521668 · Granted Dec 6, 2022

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Doped polar layers and semiconductor device incorporating same2025
Asynchronous carry-ripple adder with majority or minority gates2025
Asynchronous carry-ripple adder with majority or minority gates2025
Asynchronous carry-ripple adder with majority or minority gates2025
Perovskite-based magnetoelectric spin-orbit logic devices2025
Integrating embedded memory with logic interconnects2025
Integrating embedded memory with logic interconnects2025
Method of forming capacitors through wafer bonding2025
Method of forming capacitors through wafer bonding2025
Method of forming capacitors through wafer bonding2025
High-density low voltage non-volatile memory with unidirectional plate-line and 2025
High-density low voltage non-volatile memory with unidirectional plate-line and 2025