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Home › Method used in forming an array of vertical transistors and method used in forming an array of memory cells individually comprising a vertical transistor and a storage device above the vertical transistor

Method used in forming an array of vertical transistors and method used in forming an array of memory cells individually comprising a vertical transistor and a storage device above the vertical transistor

US Patent 11476255 · Granted Oct 18, 2022

Estimated economic value: $11,961,000 ⓘ

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