Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Reduced system memory latency via a variable latency interface

Reduced system memory latency via a variable latency interface

US Patent 11372703 · Granted Jun 28, 2022

Estimated economic value: $8,334,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Dynamically allocating memory controller resources for extended prefetching2024
Host synchronized autonomous data chip address sequencer for a distributed buffe2023
Address/command chip controlled data chip address sequencing for a distributed m2023
Refresh-hiding memory system staggered refresh2022
Address/command chip synchronized autonomous data chip address sequencer for a d2022
Speculative bank activate dynamic random access memory (DRAM) scheduler2022
Information handling system with immediate scheduling of load operations2021
DRAM bank activation management2021
Speculative bank activate dynamic random access memory (DRAM) scheduler2021
Tracking address ranges for computer memory errors2021
Address/command chip synchronized autonomous data chip address sequencer for a d2021
Performing error correction in computer memory2021