Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory-size- and bandwidth-efficient method for feeding systolic array matrix multipliers

Memory-size- and bandwidth-efficient method for feeding systolic array matrix multipliers

US Patent 11328037 · Granted May 10, 2022

Estimated economic value: $19,182,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Neural network scheduling mechanism2025
Compute optimizations for neural networks2025
Machine learning accelerator mechanism2025
Machine learning accelerator mechanism2025
Machine learning sparse computation mechanism for arbitrary neural networks, ari2025
Machine learning sparse computation mechanism for arbitrary neural networks, ari2025
Seamless place and route for heterogeneous network of processor cores2025
Dynamic precision for neural network compute operations2025
Supply voltage control systems and methods for integrated circuits2025
Graph execution using access request response dynamic batch assembly2025
Software-defined tensor streaming multiprocessor for large-scale machine learnin2025
Sparsity uniformity enforcement for multicore processor2025