Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Recalibration of PHY circuitry for the PCI express (pipe) interface based on using a message bus interface

Recalibration of PHY circuitry for the PCI express (pipe) interface based on using a message bus interface

US Patent 11327920 · Granted May 10, 2022

Estimated economic value: $19,182,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

On-package die-to-die (D2D) interconnect for memory using universal chiplet inte2025
Retimers to extend a die-to-die interconnect2025
Die-to-die interconnect protocol layer2025
Clock interpolation system for eye-centering2025
Standard interfaces for die to die (D2D) interconnect stacks2025
Valid signal for latency sensitive die-to-die (D2D) interconnects2025
System, apparatus and methods for performing shared memory operations2025
Sharing memory and I/O services between nodes2025
Link initialization training and bring up for die-to-die interconnect2025
Shared buffered memory routing2025
Shared buffered memory routing2025
Selection of processing mode for receiver circuit2025