Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Dynamic delay calibration of devices attached to bus systems utilizing time-multiplexed clock and data lines

Dynamic delay calibration of devices attached to bus systems utilizing time-multiplexed clock and data lines

US Patent 11294837 · Granted Apr 5, 2022

Estimated economic value: $106,112,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Dynamic timing calibration systems and methods2025
Dynamic timing calibration systems and methods2024
Dynamic timing calibration systems and methods2023
Low power biquad systems and methods2023
Pulse density modulation systems and methods2023
Phase-locked loop with dual input reference and dynamic bandwidth control2023
Low-power differential data transmission systems and methods2021
Low power, high bandwidth, low latency data bus2021
Sample rate conversion circuit with noise shaping modulation2021
Low delay decimator and interpolator filters2021
Low power lattice wave filter systems and methods2020
Multichannel, multirate, lattice wave filter systems and methods2020