Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory-mapped two-dimensional error correction code for multi-bit error tolerance in DRAM

Memory-mapped two-dimensional error correction code for multi-bit error tolerance in DRAM

US Patent 11218165 · Granted Jan 4, 2022

Estimated economic value: $220,790,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

SIP package structure2025
Method and system for generating magnetic resonance image, and computer readable2025
Integrated package structure2024
Clustering routing optimization method based on adaptive evolutionary algorithm 2024
Manufacturing method of chip package and chip package2024
Broadband logarithmic detector with high dynamic range2024
Automatically detecting and isolating objects in images2023
Manufacturing method of chip package and chip package2023
Passive wideband mixer2022
Unified memory organization for neural network processors2022
Selectively monitoring a network of network function chains based on probability2022
Apparatus, method, and non-transitory computer-readable medium for analyzing tra2022