Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Transistor sizing for parameter obfuscation of analog circuits

Transistor sizing for parameter obfuscation of analog circuits

US Patent 11157674 · Granted Oct 26, 2021

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Enhanced circuity security through hidden state transitions2025
On-chip voltage assignment through particle swarm optimization2025
Reducing logic locking key leakage through the scan chain2024
Charge recycling from idle circuits for improved energy efficiency of multi-volt2023
Physical layer key based interleaving for secure wireless communication2022
On-chip power supply noise suppression through hyperabrupt junction varactors2022
Work load scheduling for multi core systems with under-provisioned power deliver2022
Reduced overhead gate level logic encryption2022
Securing analog mixed-signal integrated circuits through shared dependencies2022
Physical gate based preamble obfuscation for securing wireless communication2021
Protecting analog circuits with parameter biasing obfuscation2021
Multi-states nonvolatile opto-ferroelectric memory material and process for prep2018