Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory devices and methods for managing error regions

Memory devices and methods for managing error regions

US Patent 11145384 · Granted Oct 12, 2021

Estimated economic value: $15,878,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Memory devices and methods for managing error regions2024
Flexible memory system with a controller and a stack of memory2023
Flexible memory system with a controller and a stack of memory2022
Flexible memory system with a controller and a stack of memory2021
Apparatuses and methods for memory testing and repair2020
Flexible memory system with a controller and a stack of memory2020
Apparatuses and methods having memory tier structure and recursively searching b2019
Stacked memory devices, systems, and methods2019
Memory devices and methods for managing error regions2019
Switched interface stacked-die memory architecture2019
Flexible memory system with a controller and a stack of memory2019
Switched interface stacked-die memory architecture2018